Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same

ABSTRACT

The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

FIELD OF THE INVENTION

[0001] The present invention relates generally to integrated circuitfabrication, and, more specifically, the present invention relates tothe fabrication of a super self-aligned collector for a bipolar junctiontransistor device design and process flow that allows for a compactbipolar junction transistor layout.

BACKGROUND OF THE INVENTION Description of Related Art

[0002] A bipolar junction transistor (BJT) exhibits significantresistance and substrate capacitance that raise performance issues. Inhigh-performance bipolar complementary metal oxide semiconductor(BiCMOS) processing the process flow needs to be integrated. Theaddition of high energy, high dose implantation, the use of a heavilydoped substrate layer, and the use of high temperature cycles allsignificantly degrade CMOS performance. Independent optimization of thedeep collector plug (DCP) implant and the buried layer (BL) is difficultespecially in the presence of CMOS devices.

[0003]FIG. 9 illustrates an existing BJT 10. The BJT 10 includes asubstrate 12, a collector structure 14 disposed in substrate 12, aburied layer 16, and deep trench isolation (DTI) structures 18. BJT 10also includes shallow trench isolation (STI) structures that include acollector-proximate STI (collector STI) 20, a middle- oremitter-proximate STI (emitter STI) 22, and a base-proximate STI (baseSTI) 24. Upon substrate 12, an epitaxial layer 26 is formed. An emitterstack 28 is disposed above the epitaxial layer 26. Additionally, a deepcollector plug 30, a collector tap 32 and a base tap region 34 are partof BJT 10.

[0004] Total resistivity from the collector structure to the collectortap in a BJT has a significant effect on performance. In FIG. 9, threesignificant resistivity paths exist. Although each path is depictedschematically by a dashed line, it is understood that the resistivitypaths are actually located in 3-dimensional solid space in substrate 12that is approximated by the dashed lines. A downward vertical firstresistivity path 36 passes from collector structure 14 into substrate 12toward buried layer 16. First resistivity path 36 may amount to about10% of the total resistivity between collector structure 14 andcollector tap 32. A horizontal second resistivity path 38 passes fromfirst resistivity path 36, under emitter STI 22 and toward deepcollector plug 30. Second resistivity path 38 may amount to about 30% ofthe total resistivity between collector structure 14 and collector tap32. An upward vertical third resistivity path 40 passes from secondresistivity path 38 into collector plug 30. Third resistivity path 40may amount to about 60% of the total resistivity between collectorstructure 14 and collector tap 32. For example first resistivity path 36represents a range from about 300 ohm·cm⁻² to about 700 ohm·cm⁻², secondresistivity path 38 represents a range from about 1,300 ohm·cm⁻² toabout 1,700 ohm·cm⁻², and third resistivity path 40 represents a rangefrom about 2,750 ohm·cm⁻² to about 3,250 ohm·cm⁻².

[0005] Direction changes in current flow also affect efficiency.Accordingly, because of the downward first, horizontal second, andupward third resistivity paths, efficient current flow also isdetrimentally affected due to directional changes.

[0006]FIG. 10 is a top layout schematic view depicting selectedstructures of BJT 10 without depicting elevational differences. A BJTperimeter 42 measures the BJT 10 from the outer edges 44 (FIG. 9) ofcollector STI 20 and base STI 24. Emitter STI 22 and base STI 24 arepart of a guard ring that is encompassed by BJT perimeter 42. Anexptaxial base layer perimeter 46 is also depicted that relates toepitaxial base layer 26 in FIG. 9. Emitter stack 28 is depicted by itsperimeter, and an intrinsic base region 48, is also depicted by itsperimeter as it forms substantially above collector structure 14. Otherselected structures include collector tap 32 and a base tap 50 portionof epitaxial layer 26 that is located within epitaxial base layerperimeter 46. It is noted that current flows through substrate, beneathemitter STI 22.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to further illustrate the manner in which theembodiments of the invention are obtained, a more particular descriptionof the invention briefly described above will be rendered by referenceto specific embodiments thereof which are illustrated in the appendeddrawings. Understanding that these drawings depict only typicalembodiments of the invention that are not necessarily drawn to scale andare not therefore to be considered to be limiting of its scope, theinvention will be described and explained with additional specificityand detail through the use of the accompanying drawings in which:

[0008]FIG. 1 is an elevational cross-section of a semiconductorstructure that is being fabricated into an inventive bipolar junctiontransistor (BJT) according to an embodiment of the present invention;

[0009]FIG. 2 is an elevational cross-section of the semiconductorstructure depicted in FIG. 1 after further processing;

[0010]FIG. 3 is an elevational cross-section of the semiconductorstructure depicted in FIG. 2 after further processing;

[0011]FIG. 4 is an elevational cross-section of the semiconductorstructure depicted in FIG. 3 after further processing;

[0012]FIG. 5 is an elevational cross-section of the semiconductorstructure depicted in FIG. 4 after further processing;

[0013]FIG. 6 is a plan view of one embodiment of a BJT layout whereinthe perimeters of various structures are depicted;

[0014]FIG. 7 is a plan view of one embodiment of a BJT layout whereinthe perimeters of various structures are depicted;

[0015]FIG. 8 is a flow chart that describes an inventive process flowaccording to an embodiment of the present invention;

[0016]FIG. 9 is an elevational cross-section of a semiconductorstructure according to present technique; and

[0017]FIG. 10 is a plan view of a prior art BJT layout wherein theperimeters of various structures are depicted.

DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention relates to a process of forming a bipolarjunction transistor (BJT) that has a compact, super self-alignedcollector (SAC) layout. Embodiments of the present invention includeboth monojunction and heterojunction BJT devices. A monojunction BJT ismade with materials that all have the same semiconductive band gap. Aheterojunction BJT is made with materials that all have differentsemiconductive band gaps.

[0019]FIG. 1 illustrates the beginnings of a process flow according toan embodiment. The precursor of a bipolar junction transistor 110 isfabricated from a substrate 112, that includes deep trench isolation(DTI) structures 114. Shallow trench isolation (STI) structures includea collector-proximate or first STI 116 that is spaced apart from abase-proximate or second STI 118. In an alternative embodiment, anN-buried layer 120 is embedded in substrate 112 where BJT 110 is an NPNstructure. Further, depending upon the configuration of NPN or PNP, theburied layer 120 may be selected from a P−− buried layer, a P− buriedlayer, a P buried layer, a P+ buried layer, a P++ buried layer, an N−−buried layer, an N− buried layer, an N buried layer, an N+ buried layer,and an N++ buried layer. In another embodiment, there is no buried layer120.

[0020]FIG. 2 illustrates further processing. A collector structure 122is formed in substrate 112 by ion implantation, and an epitaxial baselayer 124 is formed in substrate 112. In one embodiment, epitaxial baselayer 124 is formed by a dry anisotropic etch into substrate 112 to forma trench, followed by epitaxial growth in the trench of a material suchas monocrystalline silicon from a source such as silane. The formationof epitaxial base layer 124 such as an epitaxial monocrystalline siliconlayer is carried out according to process flows and conditions known inthe art. Epitaxial base layer 124 may be carried out by a chemical vapordeposition (CVD) process flow selected from low-pressure CVD (LPCVD),reactive-plasma CVD (RCVD), plasma-enhanced CVD (PECVD), andcombinations thereof as known in the art. By way of one non-limitingexample, the CVD process flow may be carried out in a pressure rangefrom about 10⁻² Torr, to about 2×10⁻¹ Torr. The CVD gas may be suppliedas a silane type gas or a doped silane type gas.

[0021] Thereafter, an emitter stack 126 is formed that includes emitterpolysilicon 128, an emitter cut 130 and an interlayer dielectric (ILD)layer 132. In one embodiment, an oxide layer is formed over substrate112 and epitaxial base layer 124, and patterning is done in the oxidelayer to configure ILD layer 132 and to form emitter cut 130 therein. Asa result, emitter cut 130 will facilitate formation of an intrinsic baseas set forth herein. In one embodiment, the formation of emitter stack126 is carried out after a hard mask 134 is patterned above emitterpolysilicon 128. Etching is done with hard mask 134 such that thepolysilicon film is patterned into emitter polysilicon 128.

[0022] Hard mask 134 is a material that will etch in an etch recipe thatis selective to substrate 112 and epitaxial base layer 124. For example,hard mask 134 is a nitride layer such as a silicon nitride (such asstoichiometric Si₃N₄ or the like or an Si_(x)N_(y) non-stoichiometricsolid solution). In another embodiment, hard mask 134 is a metal nitridelayer such as a refractory metal nitride. In one embodiment, the metalnitride layer is tungsten nitride. In one embodiment, the metal nitridelayer is titanium nitride. In one embodiment, hard mask 134 is selectedfrom titanium nitride, aluminum nitride, titanium-aluminum nitride, andthe like.

[0023] In one embodiment, hard mask 134 is an oxide layer such assilicon oxide. The hard mask 134, when it is an oxide layer, may be athermal oxide, a deposited oxide, or a combination thereof. In variousembodiments, the oxides are selected from silica, titania, ceria,thoria, alumina, zirconia, hafnia, and the like.

[0024] In another embodiment, hard mask 134 is an oxynitride layer suchas silicon oxynitride. Other oxynitride embodiments include oxynitridesof silicon, titanium, cerium, thorium, aluminum, zirconium, hafnium, andthe like. Oxynitride layers may be formed by thermal growth, metal oxidedeposition, followed by nitridation, and the like.

[0025] In another embodiment, the hard mask 134 is a material thatintegrates to a nitride or oxide layer that is also formed in otherregions over substrate 112. For example, several of the embodiments setforth in this disclosure may be used with a bipolar-complementary metaloxide semiconductor (BiCMOS) process flow. Accordingly, the layercomprising hard mask 134 may be utilized as protective layers over aCMOS region (not depicted) of substrate 112 during the forming ofvarious structures between first STI 116 and second STI 118.

[0026] In one embodiment, doping of emitter polysilicon 128 is carriedout once, and the presence of hard mask 134 is useful in protectingemitter polysilicon 128 from any subsequent doping or implanting processflows. For example, an emitter polysilicon film is blanket deposited andin situ doped above substrate 112. Thereafter, a hard mask material isblanket deposited, and hard mask 134 and emitter stack 126 arepatterned, either simultaneously or sequentially.

[0027]FIG. 3 illustrates further processing in which a mask 136 ispatterned in order to create a self-aligned recess 138. Mask 136 ispatterned in order to expose at least a part of first STI 116 and alsoat least a portion of hard mask 134. Thereby, first STI 116 and hardmask 134 act to create a self-aligned exposure of a portion of substrate112. In one embodiment, mask 136 is a photoresist material that is spunon, cured, and patterned. Etching is carried out through mask 136between the emitter polysilicon 128 and first STI 116 to form aself-aligned recess 138 in substrate 112, that stops at a level intosubstrate 112 to form a recess floor 140. Hard mask 134 acts as aself-aligning agent on one edge of the self-aligned recess 138. In oneembodiment, the level to which recess floor 140 cuts into substrate 112substantially eliminates the equivalent resistance of third resistivitypath 40 (FIG. 9) that would otherwise be present in BJT 110. Further,because BJT 110 is fabricated in the absence of a center- oremitter-proximate STI (FIG. 9) where emitter stack 126 share a boundarywith recess 138, the equivalent resistance of second resistivity path 38(FIG. 9) is also substantially eliminated in BJT 110.

[0028]FIG. 4 illustrates further processing. After the formation ofself-aligned recess 138 (FIG. 3), a self-aligned implanting 142 iscarried out. Mask 136, first STI 116, and hard mask 134 further act asmasking during self-aligned implanting 142. Accordingly, a self-alignedcollector tap 144 is formed in substrate 112. In one embodiment, bothetching of self-aligned recess 138 and implanting of self-alignedcollector tap 144 are done without changing masking. In one embodiment,the self-aligned etching and the self-aligned implanting 142 are done ina single tool that is first used for an etch such as a sputter etch or areactive ion etching (RIE), followed by an implanting.

[0029] Where BJT 110 is an NPN transistor, self-aligned collector tap144 (also referred to as an N source/drain (NSD) ) is N-implanted. Inother embodiments, depending upon whether BJT 110 is an NPN or a PNPtransistor, self-aligned collector tap 144 is selected from P−−collector tap, a P− collector tap, a P collector tap, a P+ collectortap, a P++ collector tap, an N−− collector tap, an N− collector tap, anN collector tap, an N+ collector tap, and an N++ collector tap. Inanother embodiment, collector tap 144 has no doping that is differentfrom that of substrate 112.

[0030]FIG. 5 illustrates further processing. Hard mask 134 (FIG. 4) isremoved by a wet etch that is selective to the emitter polysilicon 128,to epitaxial layer 124, and to self-aligned collector tap 144.Thereafter, a spacer layer is deposited and spacer etched to form aspacer 146. Spacer 146 extends into recess 138, both on one side ofemitter stack 126 and on one side of first STI 116.

[0031] Spacer 146 acts to protect and isolate substrate 112 and emitterstack 126 during further processing. In one embodiment, spacer 146 is aCMOS composite such as an oxide-nitride layer wherein the oxide layer isdeposited first and the nitride layer is deposited second, or visaversa. In another embodiment, spacer 146 is a first nitride layer and asecond oxide layer. In another embodiment, spacer 146 is a first oxidelayer and a second oxide layer, wherein the first and second oxidelayers exhibit different reactivities to etching and oxidation. Inanother embodiment, spacer 146 is a first nitride layer and a secondnitride layer, wherein the first and second nitride layers exhibitdifferent reactivities to etching and oxidation.

[0032] In one exemplary embodiment, after forming of the spacer layer,spacer etching is carried out with an anisotropic dry etching to formspacer 146. The anisotropic dry etching is a reactive ion etch (RIE),followed by an alternative wet clean as is known in the art. The spacerlayer may be selected to be either oxide, nitride, oxide-nitride,nitride-oxide, oxide-oxide, nitride-nitride, or otherwise according to aspecific process integration. For example, where BJT 110 is part of alogic structure, fabrication of an embedded memory array elsewhere onthe substrate may call for a nitride layer and an oxide layer. In thisexample, the spacer layer may be the same layer that acts to cover theembedded memory array during processing of the BJT 110.

[0033] Further processing is carried out to form an intrinsic baseregion 148 in epitaxial base layer 124. In one embodiment, thermalprocessing is used to form intrinsic base region 148. Other processingis carried out such as the formation of a bulk interlayer dielectric(ILD) layer (not depicted) over BJT 110 and contact holes (not depicted)that open to epitaxial base layer 124, to emitter stack 126, and toself-aligned collector tap 144.

[0034] One embodiment of the present invention relates to the removal ofsignificant resistivity pathways that existed in the prior art.Consequently, according to an embodiment, resistivity in BJT 110 islower that a previous BJT. Further, current flow through substrate 112between the collector structure 122 and the collector tap 144 is ahorizontal resistivity path 150 that is substantially monodirectionalalthough current flow moves through 3-dimensional solid space. Further,self-aligned recess 138 acts as a contact corridor for a metal contact(not pictured) that may include a tungsten plug, a titanium-lined recessfor a metal plug, and the like.

[0035]FIG. 6 is a top layout schematic view depicting selectedstructures of BJT 110 according to an embodiment. FIG. 6 illustratesprojections of the perimeters of various structures. A BJT perimeter 152measures the BJT 110 from the outer edges 44 of first STI 116 and secondSTI 118. In one embodiment, first STI 116 and second STI 118 are part ofa guard ring that is delineated by BJT perimeter 152. An exptaxial baselayer perimeter 154 is also depicted. Emitter stack 126 is depicted byits perimeter, and intrinsic base region 148 is also depicted by itsperimeter as it forms substantially below the emitter cut 130. It isnoted that the emitter stack perimeter 126 and the epitaxial base layerperimeter 154 intersect.

[0036] Other selected structures include the perimeter of collector tap144 and a base tap 156 perimeter portion of epitaxial base layer 124that may or may not be additionally doped.

[0037]FIG. 6 illustrates selected structures of a BJT embodiment that ismore compact that previous BJT structures. It is notable that collectortap 144 shares a substantially co-linear first boundary 158 with emitterstack 126 as accomplished by the self-aligned etch and optionalimplanting facilitated by hard mask 134 (FIG. 4).

[0038] In one embodiment it is also notable that horizontal resistivitypath 150, depicted in FIG. 5, is not encumbered by a middle STI such asin the prior art depicted in FIG. 9. Although horizontal resistivitypath 150 is depicted by a dashed line, it is understood that a givencurrent flow path between collector structure 122 and collector tap 144is substantially in a single direction.

[0039] In one embodiment, horizontal resistivity path 150 represents arange from about 300 ohm·cm⁻² to about 700 ohm·cm⁻². In other words, theamount of total impedance that is experienced is greater than about 80%in substantially in a single direction that is approximated byhorizontal resistivity path 150. In another embodiment, the amount oftotal impedance that is experienced is greater than about 90% insubstantially in a single direction that is approximated by horizontalresistivity path 150. In another embodiment, the amount of totalimpedance that is experienced is greater than about 99% in substantiallyin a single direction that is approximated by horizontal resistivitypath 150.

[0040] In one embodiment a current flow path scheme is selected thatallows for higher and shorter current flow between the collectorstructure 122 and collector tap 144 as depicted in FIG. 5. FIG. 7 is atop layout schematic view depicting selected structures of BJT 110according to an embodiment that may also be described in cross-sectionby FIG. 5. A BJT perimeter 160 measures the BJT 110 from outer edges 44(FIG. 5) of first STI 116 and second STI 118. In one embodiment, firstSTI 116 is a U-shaped guard structure that is enclosed by BJT perimeter160. Second STI 118 comprises an elongate, substantially linearlysymmetrical structure that is also enclosed by BJT perimeter 160. Anexptaxial base layer perimeter 162 is also depicted. Emitter stack 126is depicted by its perimeter, and intrinsic base region 148 is alsodepicted by its perimeter as it forms substantially below the emittercut 130 (FIG. 5). Other selected structures include collector tap 144and a base tap 164 portion of epitaxial base layer 124 (FIG. 5) that mayor may not be additionally doped. In this embodiment, collector tap 144is laid out as a U-shaped structure that allows for current flow inthree general but substantially co-planar directions between thecollector structure 122 (FIG. 5) and collector tap 144.

[0041]FIG. 7 illustrates selected structures of a BJT embodiment that ismore compact than prior art BJT structures. It is notable that collectortap 144 shares a substantially co-linear first boundary 166 with emitterstructure 126 as accomplished by the self-aligned etch and implantingfacilitated by hard mask 134 (FIG. 4). However, collector tap 144 andemitter structure 126 are not substantially co-planar as viewed inelevational cross section in FIG. 5.

[0042] It is also notable that collector tap 144 shares a substantiallyco-linear second boundary 168 with epitaxial base layer perimeter 162,as well as a substantially co-linear third boundary 170 with epitaxialbase layer perimeter 162. It is also noted that second boundary 168 andthird boundary 170 are parallel with each other.

[0043] In one embodiment it is also notable that horizontal resistivitypath 150, depicted in FIG. 5, is shorter than horizontal secondresistivity path 38, depicted in FIG. 9. However, because of the U-shapeof collector tap 144, current flows in three substantially coplanardirections. In one embodiment, horizontal resistivity path 150represents a range from about 300 ohm·cm⁻² to about 700 ohm·cm⁻². Theamount of total impedance that is experienced in these directions isgreater than about 90% of the total. In another embodiment, currentflows in three substantially coplanar directions and the amount of totalimpedance that is experienced in these directions is greater than about99% of the total directional current flow. In another embodiment,current flows in the three substantially coplanar directions and theamount of total impedance that is experienced in these directions isgreater than about 99.9%. In each selected embodiment, the current flowpaths cross at least one of first boundary 166, second boundary 168, andthird boundary 170.

[0044]FIG. 8 is a process flow diagram 800 that illustrates oneembodiment of the present invention. In one embodiment, the inventiveprocess commences with forming 810 spaced-apart first- and a secondisolation structures in a substrate. The process continues by formingelements of a bipolar junction transistor between the first and secondisolation structures. The process includes forming 820 an emitter stackbetween the first and second isolation structures. Next, the processflow forms 830 a self-aligned recess in the substrate between theemitter and the first isolation structure. Thereafter, optionalimplanting 840 of a self-aligned collector tap is accomplished in theself-aligned recess. The process continues by completing 850 a bipolarjunction transistor between the first and second isolation structures.

[0045] It will be readily understood to those skilled in the art thatvarious other changes in the details, material, and arrangements of theparts and method stages which have been described and illustrated inorder to explain the nature of this invention may be made withoutdeparting from the principles and scope of the invention as expressed inthe subjoined claims.

What is claimed is:
 1. A process comprising: in a substrate, forming afirst isolation structure spaced-apart from a second isolationstructure; forming an emitter stack between the first and secondisolation structures; in the substrate, forming a self-aligned recessbetween the emitter stack and the first isolation structure; and forminga bipolar junction transistor between the first and second isolationstructures.
 2. The process according to claim 1, further including:implanting a self-aligned collector tap in the self-aligned recess. 3.The process according to claim 1, wherein forming a self-aligned recessfurther includes: patterning a mask that exposes a portion of the firstisolation structure, a portion of the emitter stack, and a portion ofthe substrate located between the first isolation structure and theemitter stack; and etching the self-aligned recess with an etch recipethat is more selective to the first isolation structure and the emitterstack than to the substrate.
 4. The process according to claim 1,wherein forming a self-aligned recess further includes: patterning amask that exposes a portion of the first isolation structure, a portionof the emitter stack, and a portion of the substrate located between thefirst isolation structure and the emitter stack; and anisotropicallyetching the self-aligned recess with an etch recipe that is moreselective to the first isolation structure and the emitter stack than tothe substrate.
 5. The process according to claim 1, wherein implanting aself-aligned collector tap in the self-aligned recess includes:patterning a mask that exposes at least a portion of the first isolationstructure and the emitter stack; and implanting a dopant into thesubstrate that is exposed by the self-aligned recess.
 6. The processaccording to claim 1, wherein implanting a self-aligned collector tap inthe self-aligned recess includes: patterning a mask that exposes atleast a portion of the first isolation structure and the emitter stack;and implanting a dopant into the substrate that is exposed by therecess, wherein implanting results in a P−− collector tap, a P−collector tap, a P collector tap, a P+ collector tap, a P++ collectortap, an N−− collector tap, an N− collector tap, an N collector tap, anN+ collector tap, and an N++ collector tap.
 7. The process according toclaim 1, wherein forming the bipolar junction transistor between thefirst and second isolation structures includes: in the substrate,forming an epitaxial layer; forming a polysilicon film above theepitaxial layer; and patterning the polysilicon film into emitterpolysilicon.
 8. The process according to claim 1, wherein forming thebipolar junction transistor between the first and second isolationstructures includes: in the substrate, forming an epitaxial layer;forming a polysilicon film above the epitaxial layer; patterning thepolysilicon film into emitter polysilicon; and forming a spacer on theemitter stack.
 9. The process according to claim 1, wherein forming thebipolar junction transistor between the first and second isolationstructures includes: in the substrate, implanting a collector structure;in the substrate, forming an epitaxial layer; forming a polysilicon filmover the epitaxial layer; and patterning the polysilicon film intoemitter polysilicon, wherein the emitter polysilicon is disposed abovethe collector structure.
 10. The process according to claim 1, whereinforming an emitter stack includes: in the substrate, forming anepitaxial layer; forming a polysilicon film above the epitaxial layer;patterning the polysilicon film into emitter polysilicon, whereinpatterning the polysilicon film into emitter polysilicon furtherincludes: patterning a hard mask above the polysilicon film.
 11. Theprocess according to claim 1, wherein forming an emitter stack includes:in the substrate, forming an epitaxial layer; forming a dielectric layerabove the epitaxial layer; forming an emitter cut in the dielectriclayer; forming a polysilicon film above the epitaxial layer; andpatterning the polysilicon film into emitter polysilicon.
 12. Theprocess according to claim 1, further including: in the substrate,forming a buried layer.
 13. A bipolar junction transistor comprising: ina substrate, a first isolation structure spaced apart from a secondisolation structure; an emitter stack disposed above the substrate andbetween the first isolation structure and the second isolationstructure; a recess disposed adjacent and between the emitter stack andthe first isolation structure, wherein the recess exposes a collectortap.
 14. The bipolar junction transistor according to claim 13, furtherincluding: a spacer disposed on the emitter stack, wherein the spacerextends on one side thereof into the recess between the emitter stackand the first isolation structure.
 15. The bipolar junction transistoraccording to claim 13, further including: a spacer disposed on theemitter stack, wherein the spacer extends on one side thereof into therecess between the emitter stack and the first isolation structure, andwherein the spacer is selected from an oxide, a nitride, an oxide firstlayer and a nitride second layer, a nitride first layer and an oxidesecond layer, an oxide first layer and an oxide second layer, and anitride first layer and a nitride second layer.
 16. The bipolar junctiontransistor according to claim 13, further including: a spacer disposedon the emitter stack, wherein the spacer extends on one side thereofinto the recess between the emitter stack and the first isolationstructure, and wherein the spacer is further disposed on the firstisolation structure and extends into the recess.
 17. The bipolarjunction transistor according to claim 13, further including: a buriedlayer disposed in the substrate between the first isolation structureand the second isolation structure.
 18. The bipolar junction transistoraccording to claim 13, further including: in the substrate, an epitaxialbase layer disposed below the emitter stack; a collector structuredisposed in the substrate below the emitter stack; and an intrinsic basestructure disposed between the emitter stack and the collectorstructure.
 19. The bipolar junction transistor according to claim 13,further including: in the substrate, an epitaxial base layer disposedbelow the emitter stack; a collector structure disposed in the substratebelow the emitter stack; a dielectric layer disposed above the substrateand below the emitter stack, wherein the dielectric layer includes anemitter cut disposed above the collector structure; and an intrinsicbase structure disposed between the emitter cut and the collectorstructure.
 20. The bipolar junction transistor according to claim 13,further including: in the substrate, a collector tap disposed in therecess, wherein the collector tap is selected from a P−− collector tap,a P− collector tap, a P collector tap, a P+ collector tap, a P++collector tap, an N−− collector tap, an N− collector tap, an N collectortap, an N+ collector tap, and an N++ collector tap.
 21. The bipolarjunction transistor according to claim 13, wherein the substrateincludes a bipolar-complementary metal oxide semiconductor (BiCMOS)structure.
 22. The bipolar junction transistor according to claim 13,wherein the BJT is selected from a monojunction BJT device and aheterojunction BJT device.
 23. A bipolar junction transistor (BJT)layout comprising: an epitaxial base layer perimeter; an emitter stackperimeter disposed above the base layer perimeter; and a collector tapperimeter, wherein the emitter stack perimeter and the collector tapperimeter share a co-linear first boundary.
 24. The BJT layout accordingto claim 23, wherein the emitter stack perimeter and the epitaxial baselayer perimeter intersect.
 25. The BJT layout according to claim 23,wherein the collector tap perimeter shares a co-linear second boundaryand a co-linear third boundary with the epitaxial base layer perimeter.26. The BJT layout according to claim 23, further including: a base tapperimeter, wherein the base tap perimeter is enclosed by the epitaxialbase layer perimeter.